----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:31:51 06/09/2010 
-- Design Name: 
-- Module Name:    AD_Mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity AD_Mux is
    Port ( CLK_1_IN : in  STD_LOGIC;
           CLK_2_IN : in  STD_LOGIC;
           WE_1_IN : in  STD_LOGIC;
           WE_2_IN : in  STD_LOGIC;
           EN_1_IN : in  STD_LOGIC;
           EN_2_IN : in  STD_LOGIC;
           ADR_1_IN : in  STD_LOGIC_VECTOR (11 downto 0);
           ADR_2_IN : in  STD_LOGIC_VECTOR (11 downto 0);
           SEL_IN : in  STD_LOGIC;
           CLK_OUT : out  STD_LOGIC;
           WE_OUT : out  STD_LOGIC;
           EN_OUT : out  STD_LOGIC;
           ADR_OUT : out  STD_LOGIC_VECTOR (11 downto 0));
end AD_Mux;

architecture Behavioral of AD_Mux is

begin

P1:process (CLK_1_IN,CLK_2_IN,WE_1_IN,WE_2_IN,EN_1_IN,EN_2_IN,ADR_1_IN,ADR_2_IN)
begin
	if SEL_IN = '0' then
		CLK_OUT <= CLK_1_IN;
		WE_OUT <= WE_1_IN;
		EN_OUT <= EN_1_IN;
		ADR_OUT <= ADR_1_IN;
	elsif SEL_IN = '1' then
		CLK_OUT <= CLK_2_IN;
		WE_OUT <= WE_2_IN;
		EN_OUT <= EN_2_IN;
		ADR_OUT <= ADR_2_IN;
	end if;

end process;


end Behavioral;

